`include "define.v"
module IO (
    input ce,
    input ioWr,
    input clk,
    input ex_Rd,
    input [9:0]ex_Addr,
    input [31:0]wtData,
    input [31:0]Addr,
    output reg[31:0]rdData,
    output reg[15:0]ioOut
);
reg [31:0] IOcash [1023:0];
reg [31:0] Temp;
integer i=0;
initial begin
    for(i=0;i<1024;i=i+1)
    begin
        IOcash[i]=32'hffffffff;
    end
end
always @(*)
    if(ce==`Disenable)
        rdData = `Zero;
    else
        rdData = IOcash[Addr[9:0]];

always @(posedge clk) 
    if(ce==`Enable && ioWr==`Enable) begin
        IOcash[Addr[9:0]] = wtData;
        ioOut = wtData[15:0];
        end
//always @(*)
//    if(ex_Rd == `Enable)
//    begin
//     Temp = IOcash[ex_Addr[9:0]];
//     //ioOut = Temp[15:0];
//    end
endmodule